Trench isolation regions are an essential part of fabricating microelectronic circuits. The decreasing dimensions of devices and the increasing density of integration in microelectronic circuits have required a corresponding reduction in the size of isolation structures. This reduction places a premium on reproducible formation of isolation structures which provide effective isolation, while occupying a minimum amount of the substrate surface.
Trench isolation regions are typically formed by etching trenches into a substrate and filling them with a dielectric material to provide a physical barrier between adjacent structures. For example, trench isolation regions are used to electrically and/or optically isolate adjacent pixels in a pixel array, as well as isolating the pixel array from various other active components formed on an imager integrated circuit. One trench isolation region widely employed in semiconductor fabrication is the shallow trench isolation (STI) region.
In the STI technique, a plurality of trenches are formed at predefined locations in the substrate. This occurs usually through a dry anisotropic or other suitable etching process. The trenches are then filled with a dielectric such as a chemical vapor deposited (CVD) silicon dioxide (SiO2) or a high density plasma (HDP) oxide. The filled trenches are then planarized so that the dielectric remains only in the trenches and their top surface remains level with that of the substrate.
Traditional STI fabrication methods, however, have several drawbacks. One problem arises due to stress in the bottom of the trench. The rectangular corners formed at the bottom of conventional STI trenches can lead to stress and dislocations in the isolation dielectric. This can further lead to current leakage paths and contaminants, which in turn reduce the effectiveness of the isolation structure.
In addition, sidewall inversion may be a problem caused by a horizontal parasitic metal-oxide-semiconductor (MOS) device with a well acting as a gate electrode and the trench dielectric acting as a MOS gate oxide. The sidewall inversion problem is worse for n-well technology because the fixed oxide charge, normally positive, can escalate the sidewall inversion problem. Once sidewall inversion occurs, N-channel devices with an n+region abutting the same sidewall will short along the sidewall of the trench. An obvious solution is to separate the n+ region and the sidewalls of the trench, or to increase trench width. This takes up valuable space, however, decreasing the packing density required in integrated circuit chips.
Another common problem associated with the formation of the above-described trench isolation regions is that when dopants are implanted in the substrate close to the bottom and sidewalls of the trench, current leakage can occur at the junction between the active device regions and the trench. This is particularly undesirable in solid state imagers.
The dominant crystallographic planes along the bottom and sidewalls of the trench isolation regions have a higher silicon density than the adjacent silicon substrate; thereby, creating a high density of trap sites along the trench bottom and sidewalls. These trap sites are normally uncharged but become charged when electrons and holes become trapped in the trap sites. As a result of these trap sites, current generation near and along the trench bottom and sidewalls in solid state imagers can be significant. Current generated from trap sites inside or near the photodiode depletion region causes undesired dark current.
There is needed, therefore, an improved trench isolation region and a method for fabricating the same which avoids the sidewall inversion problem and which prevents current generation or current leakage in a solid state imager. A method of fabricating an imager having these characteristics is also needed.